1. Field of the Invention
The present invention relates to a negative feedback amplifier, and in particular to a negative feedback amplifier preferably used for driving a capacitive load such as vertical deflection plates or horizontal deflection plates of a CRT for an oscilloscope.
2. Description of the Related Art
FIG. 1 is a circuit diagram showing an example of a conventional amplifier for driving a capacitive load. The amplifier constitutes a balanced amplifier that amplifies a differential signal applied to input terminals IN, and outputs the amplified signal from output terminals OUT as a differential signal. A signal inputted to the input terminals IN is applied to the base of a transistor Q1 (Q2). The collector of the transistor Q1 (Q2) is connected to the base of an NPN transistor Q3 (Q4) of an output stage. Resistors R1 and R2 are input resistors, and resistors R3, R4 and R5 are emitter resistors. The collector of the NPN transistor Q3 (Q4) is connected to its base through a feedback resistor R6 (R7), and the emitter thereof is connected to a voltage source +Vb. The collector of the transistor Q3 (Q4) is further connected to the collector of a PNP transistor Q5 (Q6) and the output terminal OUT. The emitter of the PNP transistor Q5 (Q6) is connected to a voltage source +Vc through an emitter resistor R8 (R9), and the base thereof is connected through bias resistors R10 and R11 (R12 and R13) to the voltage source +Vc and the ground, respectively. In addition, the base of the NPN transistor Q3 (Q4) is connected to the base of the PNP transistor Q5 (Q6) through a capacitor C1 (C2), and the emitter of the NPN transistor Q3 (Q4) is connected to the emitter of the PNP transistor Q5 (Q6) through a capacitor C3 (C4).
With such an arrangement, a positive pulse applied to the base of the transistor Q1 conducts the transistor Q1. This in turn conducts the transistor Q5 by supplying its base with a current through the capacitor C1, as well as cuts off the transistor Q3. Thus, a charging current flows from the capacitor C3 to a load connected to the output terminal OUT via the transistor Q5. After that, the capacitor C3 is charged by a current flowing from the voltage source +Vc to the capacitor C3 through the resistor R8.
On the other hand, a negative pulse applied to the base of the transistor Q1 cuts off the transistor Q1. This in turn conducts the transistor Q3 by supplying a base current thereto, and cuts off the transistor Q5. Thus, a current flows from the load into the voltage source +Vb through the transistor Q3.
In the counterpart circuit comprising the transistors Q2, Q4 and Q4, a current flows into or flows from the load via the output terminal OUT in opposite directions to those of the currents of the above circuit.
This circuit, however, has a disadvantage that the switching on operation of the transistor Q3 is liable to be delayed because of insufficient driving power of the transistors Q3 and Q5. To speed up the switching, the following conditions must be satisfied: the value of the resistor R8 is reduced; standing currents (quiescent collector currents) of the transistors Q3 and Q5 are increased; and the value of the feedback resistor R6 is reduced. Therefore, the transistors Q3-Q6 in the output stage must have large collector dissipations.
Considering this, a circuit that can provide enough driving power without increasing a standing current of the output stage is arranged as shown in FIG. 2. In this figure, the collector of an input stage transistor Q1 (Q2) is connected to the base of a PNP transistor Q7 (Q8). The collector of the transistor Q7 (Q8) is connected to a reference potential, and the emitter thereof is connected to the base of a transistor Q3 (Q4), as well as to the emitter of an NPN transistor Q9 (Q10) through a resistor R14 (R15). The collector of the transistor Q9 (Q10) is connected to a voltage source +Vd, and the base thereof is connected to an output terminal OUT through a resistor R6 (R7). The base of the transistor Q7 (Q8) is connected to the base of the transistor Q9 (Q10) via Zener diodes D1 (D2) so that the two bases has a fixed potential difference.
With this arrangement, the output stage can be sufficiently driven because an amplifier comprising the complementarily connected transistors Q7 and Q9 (Q8 and Q10) is interposed between the input stage transistor Q1 (Q2) and the output stage transistors Q3 and Q5 (Q4 and Q6).
In such a circuit arrangement, however, only an insufficient standing current flows through the input transistor Q1 (Q2), which deteriorates a high frequency band characteristic because of small amplification in the high frequency region such as above several tens of megahertz. In addition, an output voltage decreases in the high frequency region when a capacitive load is connected to the output terminals OUT. the reason for this is as follows: When a load current flowing through a capacitive load connected to the output terminals OUT increases in the high frequency region, a standing current cannot follow the increase in the load current in the high frequency region because the standing current flowing through the output stage is limited by the resistor R8 (R9). Furthermore, in a large amplitude output, the dissipation power of the output stage transistors Q3 and Q4 alters depending on the output signal. This induces changes in temperature and an emitter-to-base voltage V.sub.BE, which causes waveform distortion such as sag and rounding in the output signal. Still further, in a large amplitude output, the output stage transistors Q3 and Q5, and Q4 and Q6 are saturated, thereby deteriorating high-speed response characteristics.